1. Field of the Invention
This invention relates to an electrically rewritable nonvolatile semiconductor memory device and more particularly to the technique for enhancing the read/verify operation speed in a multivalue NAND flash memory, for example.
2. Description of the Related Art
The number of memory cells connected to a bit line is increased with an increase in the memory capacity of a semiconductor memory device and the pitch of the bit lines is narrowed with a reduction in the chip size. Therefore, the capacitance associated with the bit line and the capacitance between the bit lines are steadily increased.
In a NAND flash memory, in order to reduce the influence of the capacitive coupling due to the parasitic capacitance between the bit lines, one of the adjacent two bit lines is shielded at the time of charging/discharging the bit line. For example, a bit line of an odd-numbered address is shielded when a bit line of an even-numbered address is accessed and a bit line of an even-numbered address is shielded when a bit line of an odd-numbered address is accessed (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. H04-276393).
However, since the load capacitance of the bit line becomes larger as described above and the bit line is charged by use of a clamp circuit having small current driving ability in order to suppress an increase in the chip occupied area, time for charging the bit line becomes long, thereby causing the read/verify operation speed to be lowered. Further, since the bit line of large load capacitance is discharged via a cell transistor whose current driving ability is made small because of miniaturization when the bit line is discharged, long time is required for discharging and the read/verify operation speed is lowered in this respect.